1. Field of the Invention
The present invention relates generally to integrated sampling circuits, and more particularly to single-supply sampling circuits that sample between a positive and negative voltage range.
2. Background of the Invention
The importance of electronic circuitry and the continual reduction of chip geometries in which these circuits are realized is well understood. In designing various electrical circuits, the substrate or wafer area requirements of the circuits are oftentimes very important because of size constraints in which the chip may be located as well as the cost of manufacturing the chip.
As processes and devices move towards smaller geometries to save space and reduce cost, supply and input voltages levels have to be reduced. However, most real world applications continue to have higher voltage transducer signals. Conventional methodologies to sample these types of real world signals generally require supply voltages that are beyond the input signal voltage range. Oftentimes, the supply voltage requirements of the semiconductor process and the real word signals are in conflict, resulting in many existing designs requiring multiple supply voltages. In particular where signal swings are symmetric around a ground potential, existing integrated circuit designs for the most part require both positive and negative supply voltages. The inclusion of these supply voltages has undesirable system cost and complexity implications.
An alternative to multiple supply voltages is to attenuate real world signals to the voltage levels supported by modern semiconductor processes. The use of voltage attenuators, however, has several disadvantages including requiring higher transducer current to drive the attenuator and more importantly increased system noise.
Therefore, what is needed is a device and method that addresses the above-described disadvantages of the prior art including the use of multiple power supplies and input attenuation resistors.